1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory in which data of two bits or more can be stored per one memory cell, and relates to a manufacturing method of the same.
2. Description of the Related Art
A nonvolatile semiconductor memory in which data of two bits can be stored per one memory cell has been developed in order to achieve high integration of the nonvolatile semiconductor memory, reported in “Embedded Twin MONOS Flash Memories with 4 ns and 15 ns Fast Access Times” by Tomoko Ogura et al., (2003 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 207-210). FIG. 1 is a cross sectional view of such a conventional nonvolatile semiconductor memory. As shown in FIG. 1, the conventional nonvolatile semiconductor memory contains a memory cell 102 formed on the surface of a silicon substrate 101.
In the memory cell 102, source/drain regions 106 are formed in the surface of the silicon substrate 101, a gate insulating film 103 is formed on the region on the silicon substrate 101 between the source drain regions 106. A control gate 104 as a word line is formed on the gate insulating film 103. A silicide layer 105 is provided on the control gate 104. Moreover, memory gates 108 are provided on both sides of the control gate 104. Here, ONO films (Oxide Nitride Oxide films) 107 are respectively formed between the control gate 104 and each of the memory gates 108, and between each of the memory gates 108 and the silicon substrate 101. In addition, the source/drain regions 106 are connected with a bit line (not shown) in an upper layer through a contact (not shown).
In such a nonvolatile semiconductor memory, a binary data can be stored by selecting a charged state of the nitride film in the ONO film 107, that is, by depending on whether electrons are stored in the nitride film or not. Then, by controlling the charged state of each of the ONO films 107 on both sides of the control gate 104 independently, the data of two bits 102 can be stored in one memory cell. It should be noted that the memory gate 108 is provided in order to simplify injection and drawing out of the electrons into and from the ONO film.
However, the conventional nonvolatile semiconductor memory has following problems. That is, in the conventional nonvolatile semiconductor memory, the control gate 104 and the memory gate 108 are electrically separated. Therefore, it is necessary to independently control the control gate 104 and the memory gate 108. As a result, a control circuit in the nonvolatile semiconductor memory becomes complex and large. Also, a silicide layer is not formed on the memory gate 108, so that the memory gate 108 has high resistance. Therefore, the conventional nonvolatile semiconductor memory is unsuitable for high-speed operation. For this reason, a metal wiring (not shown) is provided in an upper wiring layer, and an contact (not shown) is provided for every tens of the memory cells to connect the memory gate 108 with the metal wiring. Thus, the entire wiring resistance is decreased. As a result, a layout area of the nonvolatile semiconductor memory shall be increased.
To solve such a problem, a nonvolatile semiconductor memory is disclosed in Japanese Laid Open Patent Application (JP-P2001-156188A), in which a memory gate is connected with a control gate. FIG. 2 is a cross sectional view of the conventional nonvolatile semiconductor memory. As shown in FIG. 2, this conventional nonvolatile semiconductor memory is composed of a memory cell formed on the surface of a p-type semiconductor substrate 111. In the memory cell, an n−-type diffusion layer 120 and an n+-type diffusion layer 121 are formed as source/drain regions on the surface of the p-type semiconductor substrate 111. A gate insulating film 112 and a control gate 113 are provided on the region between the source/drain regions. Charge storage layers 114 are provided on the sides of the control gate 113 above the n-type diffusion layer 120. The charge storage layer 114 is an ONO film, in which a first oxide film 115, a nitride film 116, and a second oxide film 117 are laminated in this order. Electrons are stored in the nitride film 116. Also, a memory electrode 118 is provided on the charge storage layer 114. A sidewall insulating film 119 is provided on the each of the memory gates 118. The top end of the memory gate 118 is as high as that of the charge storage layer 114. A silicide 122 is formed on the control gate 113, the charge storage layer 114, and the memory gate 118 in the nonvolatile semiconductor memory.
In the conventional nonvolatile semiconductor memory shown in FIG. 2, the memory gate 118 is connected with the control gate 113 through the silicide film 122. Therefore, the control gate 113 and the memory gate 118 can be driven by a common control circuit. Also, the upper layer wiring and the contact are not necessary to reduce the resistance of the memory gate 18. As a result, the layout area of the nonvolatile semiconductor memory can be decreased.
However, the above-mentioned conventional technique has following problems. In the conventional nonvolatile semiconductor memory shown in FIG. 2, the silicide 122 bridges the memory gates 118 and the control gate 113 on the charge storage layer 114. However, the charge storage layer 114 is an insulating layer. It is not possible to form the silicide layer on the insulating layer by using metals such as cobalt (Co), nickel (Ni), and palladium (Pd) that are diffused in the silicon containing layer on reaction with the metals and silicon (Si). In other word, the silicide film 122 cannot be provided by forming a metal layer made of Co, Ni, Pd, and the like on the charge storage layer 114 by sputtering, and by reacting the metal layer with silicon included in the memory gate 118 and the control gate 113. This is because atoms in the metal layer such as Co, Ni, Pd and the like are undesirably diffused in the control gate 113 or remained on the memory gate 118 with no reaction.
On the other hand, in case of titanium (Ti), Si atoms are diffused on the reaction of titanium with silicon, and is hardly moves itself. Therefore, when a Ti layer is formed on the charge storage layer 114 for the silicide film, the silicide layer may be able to be provided on the charge storage layer 114 through self-increasing since the silicon atoms are diffused from the memory gate 118 and the control gate 113. However, occasionally, the silicide layer might not be able to be provided well, and reliability is low. Moreover, in the nonvolatile semiconductor memory shown in FIG. 2, the memory gate 118 is connected with the control gate 113 by only the silicide film. Therefore, connection reliability is low.